Semiconductor device having wires and insulator layers with via-studs

ABSTRACT

The semiconductor device is provided with an insulator layer having a via-stud on a semiconductor substrate, the via-stud being formed in a via-hole through a barrier layer formed of an inorganic compound layer or a high melting point metal layer formed on an inner surface of the via-hole, the via-stud being made of the same metal as a metal composing the barrier layer. The semiconductor device can be obtained by forming the barrier layer on the inner surface of the via-hole in the semiconductor substrate, then treating the substrate with a treatment solution containing a complex forming agent, immersing the treated substrate into an electroless plating solution, bringing a member made of the same metal as a metal formed by the electroless plating in contact with the electroless plating solution, and electrically connecting the member to the barrier layer to perform electroless plating.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a novel plating method andparticularly to a plating method to be used for forming wiring on asubstrate in a semiconductor device, such as an LSI or the like.

[0002] Both an aluminum sputtering method and a tungsten CVD method havebeen used for depositing a metal film to be used as wiring in asemiconductor device. However, the wiring is expected to be made fineras a result of continuing progress in achieving higher integration ofLSI devices, and, consequently, there arise problems caused by delay insignal transfer speed due to high resistivity and a decrease inreliability due to low migration resistance when a wiring material suchas aluminum, tungsten or the like is used. Although copper is expectedto be used as a wiring material in place of the conventional materialbecause it is capable of realizing low resistivity and highelectro-migration resistance, there are many problems to be solved ifthis wiring material is to be used.

[0003] In a case of using copper as the wiring material, it is generallydifficult to use a dry etching method, which is used to form aluminumwiring, as the wiring forming method. Therefore, a method is employed inwhich an insulation film is formed on a substrate in advance, portionsof the insulation film corresponding to locations of the wiring orinter-layer connecting conductive bodies are machined to produce adepressed shape, and then the depressed portions are filled with copper.

[0004] As a filling method, there is a method of selectively fillingonly the depressed portion, but a more common method is one in which thewhole surface of the substrate, including the depressed portions, ismetallized, and then chemical-mechanical polishing (CMP polishing) isperformed on the surface to remove the surface layer. As a metallizingmethod for filling the depressed portions, there are dry metallizingmethods, such as a sputtering method, a chemical vapor deposition method(CVD method) and the like, and wet metallizing methods, such aselectroless plating, electrolytic plating and the like.

[0005] In recent years, much attention has been focused on a processcombining the wet metallizing method and CMP polishing, because the wetmetallizing method is advantageous in that it has a good fillingcapability with respect to very small depressed portions for forminghigh density wiring. Japanese Patent Application Laid-Open No.8-83796discloses a method of filling wiring trenches through electrolessplating using silver, copper, gold, nickel, cobalt or palladium.

[0006] In order to achieve a reduction in the resistivity of wiring to avalue lower than that of aluminum wiring, it is considered that onlysilver, copper and gold may be used. In a case of using such a metal, apalladium seed layer is formed by collimator sputtering, and then anelectroless plating film is formed on the palladium seed layer. In sucha method, the process of forming the palladium seed layer by collimatorsputtering becomes a bottleneck, and, accordingly, it is impossible withthis procedure to make the wiring sufficiently fine. In addition,palladium will easily react with the electroless metal to easilypenetrate into the wiring metal, which causes an increase in theresistivity. This result is inconsistent with the objective of employinga low resistive metal for replacing aluminum.

[0007] Further, Japanese Patent Application Laid-open No. 6-29246discloses a method in which a substance serving as a catalyst forelectroless plating reaction is added to the inside of trenches andholes through wet treatment, and then the inside of the holes are filledwith a metal by electroless plating. In this case, palladium is used forthe catalyst. For purposes of reducing the resistivity of wiring to avalue lower than that of aluminum wiring, electroless plating of copperis the best method. However, palladium easily reacts with copper toincrease the resistivity, and consequently the essential object ofreducing the resistivity can not be attained with this procedure.

[0008] Further, there is a well known method in which a zinc oxide layeris formed in a silicon oxide film (an insulator film) having very smalldepressed portions formed through spray pyrolysis, and palladium or thelike is substitutively plated while the zinc oxide layer is beingmelted, and then a copper or gold film is formed by electrolytic platingor electroless plating using the palladium as a seed layer. However,since palladium is used in this method, similar to in theabove-mentioned method, there is a problem in that the resistivity ofthe wiring metal is increased. In addition to this, there is apossibility that the mixing of zinc deteriorates the characteristic ofthe element.

[0009] Furthermore, Japanese Patent Application Laid-open No.7-283219,Japanese Patent Application Laid-open No. 7-122556 and Japanese PatentApplication Laid-Open No. 8-83796 disclose methods in which a titaniumfilm, a titanium nitride film and a tantalum film are successivelyformed on a surface of an insulator layer having depressed portionsformed thereon, and then copper is electrolytically plated on the filmsto form wiring. In this case, in contrast to the aforementioned methods,it seems that no increase in resistivity of the copper wiring by adifferent kind of element, such as palladium, is caused. However,because the electric resistivity of the multilayer thin film oftitanium, titanium nitride and tantalum is large, the method has adisadvantage in that the capability of filling the depressed portions ispoor when the multilayer thin film is used as a cathode for electrolyticplating.

[0010] In electrolytic plating, the application of a uniform electricfield is required in order to obtain a uniform deposition. However, in acase of a cathode having a high resistivity, as described above, it isdifficult to apply the electric field to a portion near the bottom ofthe depressed portion. Particularly, it is anticipated that the fillingcapability is deteriorated as the depressed portion is narrowed anddeepened (the aspect ratio is increased). This is a fatal weakness ofthis method for forming fine wiring.

[0011] Although various methods of filling depressed portions with ametal through use of a wet metallizing method, which is advantageous infilling very small depressed portions, have been studied, as describedabove, each of the methods has problems. Since the object is to reducethe resistivity of wiring to a value lower than that of aluminum wiring,alternative metallic materials are limited to copper, silver and gold.

[0012] However, since these metals likely react with a insulator layeror silicon, four surfaces of the metal wiring need to be protected by abarrier layer made of an electric conductor. materials capable offunctioning as a metallic barrier layer, are metal nitrides, such astitanium nitride, tungsten nitride, tantalum nitride and so on, highmelting point metals, such as tantalum, tungsten and so on, and alloysof the high melting point metals.

[0013] However, since the metal nitrides, the high melting point metalsand the alloys of the high melting point metals are inactive toelectroless plating reaction, it has been impossible to performelectroless plating directly on the metal nitride, the high meltingpoint metal or the alloy.

[0014] Further, since the metal nitrides, the high melting point metalsand the alloys of high melting point metals have a large electricresistivity, it has been impossible to perform electrolytic platingdirectly on a metal nitride, a high melting point metal or an alloythereof.

[0015] Therefore, in order to fill very small depressed portions withplating, it is necessary to form a seed layer to serve as a catalystthrough electroless plating of copper, palladium or the like. A seedlayer formed through a dry metallizing method is poor in providinguniform deposition onto the bottom portion and the side wall of a verysmall trench, which is an obstacle to making the wiring finer.

[0016] Accordingly, in regard to a method of forming the seed layer, amethod which is excellent in uniform deposition capability for replacingthe dry metallizing method is needed. Although there is a studyconcerning a substitution plating method using palladium for forming aseed layer, this method has a problem in the formation of finer wiringbecause palladium increases the resistivity of the wiring, as describedabove.

[0017] Although there is a study concerning a substitution platingmethod using copper, this method has a problem of poor adherence.Further, these substitution plating methods have a fatal problem in thatsufficient reliability can not be secured because elution of the barrierlayer occurs as the plating metal is deposited.

SUMMARY OF THE INVENTION

[0018] An object of the present invention is to provide a semiconductordevice in which very small depressed portions of via-holes or trencheson a substrate are directly filled with a metal, without forming anyseed layer of high resistivity, by using a dry metallizing method, andto provide a module and a large-scaled computer employing thesemiconductor devices.

[0019] Another object of the present invention is to provide a method ofmanufacturing a semiconductor device, which method is excellent ineffecting uniform deposition in very small depressed portions ofvia-holes or trenches on a substrate and filling the via-holes or thetrenches with a metal without elution of a barrier layer during theprogress of the plating reaction.

[0020] In accordance with the present invention, after treating anelectric conductor surface of a barrier layer made of an inorganiccompound or a high melting point metal and covering a surface of adielectric layer on an LSI semiconductor substrate with a treatingsolution containing a complex forming agent, the electric conductor iselectrically connected with a substance in which electroless platingreaction is carried out or a substance in which electroless platingreaction is to be carried out, and thereby the plating metal is formedon the electric conductor surface by applying electroless plating. Allof the via-holes or trenches formed in the insulator layer are filledwith the plating metal.

[0021] The present invention is characterized by a semiconductor devicecomprising an insulator layer having a hole and/or a trench for forminga via-stud and/or a wire therein on a semiconductor substrate,preferably on an LSI semiconductor substrate, wherein the via-studand/or the wire are formed in the via-hole and/or the trench through abarrier layer made of an inorganic compound or a high melting pointmetal formed on an inner surface of the via-hole and/or the trench, thevia-stud and/or the wire being formed of the same metal as a metalcomposing the barrier layer.

[0022] Further, the present invention is characterized by asemiconductor device comprising insulator layers with at least onevia-stud and insulator layers with wiring disposed on a semiconductorsubstrate, preferably on an LSI semiconductor substrate, the insulatorlayers having a via-stud and the insulator layers having wiring beingalternately arranged on the substrate. Therein, the whole via-stud inaccordance with the present invention is formed of the same metal as ametal composing a barrier layer and is formed through electroplatingafter electroless plating or through electroless plating.

[0023] The present invention is characterized by a resin sealedsemiconductor device of the surface mounting type or the non-surfacemounting type which is sealed by a composition containing epoxy resin,spherical quartz particles and silicone polymer, or not containingsilicone polymer. The content of the spherical quartz particles is morethan 70 weight %, preferably 80 to 95 weight %, of the total weight ofthe composition. In accordance with the present invention, thecomposition used for a low-profile semiconductor device having athickness thinner than 1.5 mm, such as a logic or memory semiconductordevice, contains quartz particles of 82 to 90 weight %, but does notcontain a silicone polymer, and more than 90% of the quartz particlesare spherical quartz particles and 3 to 10% of the quartz particles arenon-spherical (cubic) quartz particles.

[0024] Further, in accordance with the present invention, a logic ormemory semiconductor device having a thickness greater than 1.5 mm, suchas a general QPF of a surface mounting type, a DILP of a non-surfacemounting type for the logic device and an SOJ or a TSOP of a surfacemounting type, a DIPL of a non-surface mounting type for the memorydevice is sealed with an epoxy resin composition containing a filler,preferably quartz particles, of 75 to 81% and silicone. It is preferablethat the filler is composed of 60 to 80% of melt spherical quartzparticles having grain size of 5 μm to 100 μm and the remainder of cubicquartz particles (pulverized quartz particles) having a grain sizesmaller than 5 μm, preferably smaller than 3 μm. It is preferable thatthe content of the spherical quartz particles is 65 to 75%.

[0025] The present invention is characterized by a module comprising amultilayer thin film wiring substrate composed of a plurality oflaminated insulator layers, each of the insulator layers having a wiringlayer on a surface; and a semiconductor device mounted on the wiringsubstrate, wherein the semiconductor device is the semiconductor devicedescribed above.

[0026] The present invention is characterized by a large-scaled computercomprising a module substrate mounted on a printed wiring board, themodule substrate being connected to the printed wiring board throughconnecting pins; a multilayer thin film wiring substrate mounted on themodule substrate, the multilayer thin film wiring substrate having aplurality of laminated insulator layers, each of the insulator layershaving a wiring layer; and the above-mentioned semiconductor devicemounted on the wiring substrate.

[0027] The present invention is characterized by a semiconductor devicecomprising an insulator layer having a via-stud on a semiconductorsubstrate, wherein the via-stud is formed in a via-hole through abarrier layer made of an inorganic compound or a high melting pointmetal formed on an inner surface of the via-hole, the diameter of thevia-stud being smaller than 0.3 μm.

[0028] The present invention is characterized by a semiconductorsubstrate plating method of forming a plating metal on a surface of aconductor layer of a semiconductor substrate using an electrolessplating solution, the semiconductor substrate comprising an insulatorlayer made of a dielectric having a trench or a via-hole formed on thesemiconductor substrate; and a conductor layer of a barrier layer madeof an inorganic compound or a high melting point metal covering thesurface of the insulator layer including the side surfaces and thebottom surface of the trench or the via-hole, the method comprising thesteps of treating the surface of the conductor layer with a treatingsolution containing a complex forming agent in the electroless platingsolution; then electrically connecting the surface of the conductorlayer to a substance for carrying out an electroless plating reaction ora substance for which an electroless plating reaction is to be carriedout; and performing electroless plating onto the surface of theconductive layer to fill the trench or the via-hole with the metal andto further deposit the metal on the trench or the via-hole filled withthe metal.

[0029] Further, the present invention is. characterized by asemiconductor substrate plating method in which, after performingelectroless plating onto the surface of the conductive layer, the trenchor the via-hole is filled with the metal and the metal is deposited onthe trench or the via-hole filled with the metal through electroplating,similar to the above.

[0030] It is preferable that the electroless plating described above iscopper plating, and the thickness of the plated layer is 1 to 100 nm.

[0031] The inorganic compound or the high melting point metal describedabove is a conductor, and it is preferable that the conductor is any onekind of titanium, tantalum, tungsten, cobalt, and nitrides of thesemetals, and alloys of titanium, tantalum, tungsten or cobalt.Particularly titanium, tantalum, tungsten or cobalt corresponds to thelatter and has a melting point above 1490° C.

[0032] It is preferable when the complex forming agent isethylene-diamine-tetra-acetate, and the electroless plating iselectroless copper plating, and the treating solution before performingthe electroless copper plating is an aqueous solution which contains atleast the above-described ethylene-diamine-tetra-acetate of 0.001 to 1mol/l and hydrogen peroxide of 0 to 1 mol/l.

[0033] It is preferable when the substance electrically connected to theconductor layer is the same metal as a plating metal deposited by theelectroless plating.

[0034] That is, the conductor layer is formed of a substance on whichthe plating metal cannot be formed by electroless plating, as describedpreviously. However, the present invention makes it possible to form theplating metal on the conductor layer by treating the substrate with atreating solution containing a complex forming agent, immersing themetallic member made of the plating metal formed by the electrolessplating, and electrically connecting the metallic member to theconductor layer.

BRIEF DESCRIPTION OF DRAWINGS

[0035]FIG. 1 is a process flow diagram showing in successive schematiccross-sectional views respective processes of a method of plating asubstrate in accordance with the present invention.

[0036]FIG. 2 is a process flow diagram showing in successive schematiccross-sectional of a method of plating a substrate in accordance withthe present invention.

[0037]FIG. 3 is a process flow diagram showing in successive schematiccross-sectional views respective processes of a method of plating asubstrate in accordance with the present invention.

[0038]FIG. 4 is a cross-sectional view showing a semiconductor device inaccordance with the present invention in which a multilayered wiringlayer is formed.

[0039]FIG. 5 is a perspective view showing a resin sealing semiconductordevice of the surface mounting type in accordance with the presentinvention.

[0040]FIG. 6 is a process flow diagram showing the process ofmanufacturing a thin film multilayer wiring substrate.

[0041]FIG. 7 is a schematic cross-sectional view showing a mountingstructure using a thin-film multilayer wiring substrate in accordancewith the present invention.

[0042]FIG. 8 is a schematic -cross-sectional view showing an example ofthe mounting of a large-scaled computer board in accordance with thepresent invention.

[0043]FIG. 9 is a cross-sectional view showing a semiconductor devicehaving a multilayered wiring layer in accordance with the presentinvention.

[0044]FIG. 10 is a cross-sectional view showing the structure of flipchip mounting in accordance with the present invention.

[0045]FIG. 11 is a cross-sectional view showing a ball grid array typesemiconductor device in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] There are various combinations of a barrier layer and electrolessplating to which the present invention can be applied, as describedabove. However, the description will be directed to a case wheretitanium nitride is used for the barrier layer, and electroless copperplating is used for forming the seed layer.

[0047] An insulator layer of a dielectric material is formed on asilicon substrate, and after forming trenches in the insulator layer, abarrier layer made of a dielectric of titanium nitride is formedthereon. The sputtering method or the CVD method is used for forming thebarrier layer. The CVD method is advantageous from the viewpoint ofuniform deposition in the trench. However, in contrast to a seed layer,the barrier layer does not need to have a uniform film thickness betweenthe surface and the inside of the trench, but what is needed is at leastto secure a thickness capable of exerting the barrier function.Therefore, the sputtering method can be also employed.

[0048] After that, the seed layer is formed on the barrier layersurface. It is preferable when the seed layer has a uniform filmthickness both on the surface and inside the trench. The reason for thisis that, if the seed layer is not formed to a uniform film thicknessboth on the surface and inside the trench, the resistance of the seedlayer becomes different between the surface and the inside of trenchwhen electroplating for filling the trench is performed. Therefore,since the resistance of the seed layer inside the trench having athinner film thickness becomes higher than the resistance of the seedlayer on the surface having a thicker film thickness, it is difficult toapply the electric field to the inside of trench, and, accordingly, thetrench can not be filled with the plating metal.

[0049] With the conventional sputtering method, it is impossible to forma seed layer having a uniform film thickness both on the surface andinside the trench. In the conventional method not employing the presentinvention, any difference in the resistances between the surface and theinside of trench is apparently made small by increasing the sputteredfilm thickness. However, when the sputtered film thickness is increasedto a point where it is too thick, an opening portion of the trench orthe hole is blocked to form a void.

[0050] The present invention is a revolutionary new method of forming aseed layer which can form a uniform thickness film even on a complexshaped surface through electroless copper plating. The reaction of theelectrolytic copper plating can be expressed by the following chemicalreaction formula (Chemical formula 1).

Cu²⁺(L)+2HCHO⁻+20H⁻→Cu+2HCOO⁻+2H₂O+H₂+L  (Chemical formula 1)

[0051] There, L is a complex forming agent for forming copper and acomplex, and ethylene-diamine-tetra-acetate (hereinafter referred to asEDTA) is often used for the complex forming agent.

[0052] This reaction selectively progresses on a metal such as copper,palladium or the like. This is because the metal exerts catalyticactivity to oxidation reaction of formaldehyde. Formaldehyde releases anelectron when it is oxidized, and a copper ion receives the electron soas to be reduced to metallic copper.

[0053] However, titanium nitride of the barrier layer is inactive to theelectroless copper plating reaction. Therefore, even if the siliconsubstrate having a titanium nitride layer formed on the surface isimmersed into an electroless copper plating solution, plating reactionis not progressed, and, consequently, copper is not deposited on thebarrier surface.

[0054] The inventors of the present invention found that electrolesscopper plating could be performed directly on a titanium nitride surfaceformed on a surface of a substrate by treating the titanium nitridesurface with a surface treating solution containing EDTA, thenelectrically connecting the barrier layer of the substrate with a copperplate and immersing the substrate into an electroless copper platingsolution together with the copper plate.

[0055] Therein, it is preferable that, after the surface treatment withthe EDTA solution, the substrate is directly immersed into theelectroless copper plating solution without first carrying out a waterwashing process. Further, it is preferable when the electricallyconnected copper plate has a surface area larger than that of the wafersubstrate to be plated, and it is better when the surface area of thecopper plate is more than 1.5 times as large as that of the substrate.

[0056] As described above, the seed layer can be formed on the surfaceof the barrier layer directly through electroless plating by treatingthe barrier layer surface to become the base of the electroless platingwith the surface treating solution containing the complex forming agentwhich forms a plating metal and a complex of the electroless platingsolution in the next process, then electrically connecting the barrierlayer of the substrate to be plated to a substance progressing platingreaction, and immersing them into the electroless plating solution. Thefilm thickness distribution of the seed layer formed by the electrolessplating is within ±5% in both the surface portion and the inside portionof the trench, and accordingly the uniformity of the film thickness isvery good.

[0057] In addition to the above-mentioned electroless copper plating,electroless nickel plating, electroless gold plating, and electrolesscobalt plating can be also employed for forming a seed layer for formingsubstrate wiring.

[0058] In regard to the insulator layer in accordance with the presentinvention, a film formed, for example, through a thermal CVD method andmade of a Si-containing compound such as SiO₂, BPSG, PSG, BSG, AsSG,NSG, SOG, LTO, SiN, SiON, SiOF or the like, an organic group lowdielectric film made of amorphous Teflon(poly-tetra-fluoro-ethylene),BCB (benzo-cyclo-butane), parylene, flare(fluorinated-arylene-ether) orthe like, or a laminated film of these films is usable.

[0059] The method of forming the insulator layer will be described belowin detail.

[0060] (1) “Condition of forming SiO₂ film through thermal CVD”

[0061] Gas: SiH₄/O₂/N₂=250/250/100 sccm

[0062] Pressure: 13.3 Pa

[0063] Substrate heating temperature: 420° C.

[0064] (2) “Condition of forming SiN film through plasma CVD”

[0065] Gas: SiH₄/N₂O=50/10 sccm

[0066] Pressure: 330 Pa

[0067] RF: power 190 W

[0068] Substrate heating temperature: 400° C.

[0069] (3) “Cohdition of forming TEOS-SiO₂ film through plasma CVD”

[0070] Gas: TEOS=50 sccm

[0071] Pressure: 330 Pa

[0072] RF: power 190 W

[0073] Substrate heating temperature: 400° C.

[0074] (4) “Condition of forming SiON film through ECR plasma CVD”

[0075] Gas: SiH₄/N₂O=50/25 sccm

[0076] Pressure: 330 Pa

[0077] RF: power 800 W

[0078] Substrate heating temperature: 360° C.

[0079] (5) “Condition of forming SiO₂ film through magnetron spattering”

[0080] Gas: Ar=100 sccm

[0081] Pressure: 0.4 Pa

[0082] RF: power 5 kW

[0083] Substrate heating temperature: 150° C.

[0084] In regard to the technology for forming a via-hole to became acontact hole, a lithography technology and an etching technology areused. A contact hole having a hole diameter smaller than 0.3 μm,preferably 0.15 to 0.25 μm, can be formed in the insulator layerpreferably under the following condition.

[0085] Gas: C₄F₈/CO/Ar=10/100/200 sccm

[0086] Pressure: 6 Pa

[0087] RF: power 1600 W

[0088] Substrate heating temperature: 20° C.

[0089] Preferable condition of chemical-mechanical polishing (CMP) ofcopper is as follows.

[0090] “CMP condition of Cu (+Tin/T)”

[0091] Polishing pressure: 100 g/cm²

[0092] Number of rotations: Surface plate 30 rpm

[0093] Polishing head: 30 rpm

[0094] Polishing pad: IC-1000 (a trademark)

[0095] Sultry: H₂O₂ base (containing alumina)

[0096] Flow rate: 100 cc/min

[0097] Temperature: 25 to 30° C.

[0098] [Embodiment 1]

[0099]FIG. 1 is a process flow diagram showing a method of plating anLSI silicon substrate in accordance with the present invention.Initially, as shown in FIG. 1 in process (a), an insulator film 2 wasformed by depositing SiO₂ to 0.9 μm thickness on an LSI siliconsubstrate 1 through the thermal CVD method, and via-holes 3 reachingdown to the LSI silicon substrate 1 were formed in the insulator film 2.The diameter of each via-hole 3 was 0.3 μm. After that, titanium nitride4 was deposited to form a barrier layer which covered the whole surfacefrom the via-hole 3 to the surface of the insulator film. In general, anordinary method of electroless plating can not directly form a platingmetal on the surface of a titanium nitride layer.

[0100] Next, the substrate was immersed into an aqueous solutioncontaining EDTA of 0.1 mol/l and hydrogen peroxide of 0.08 mol/l attemperature of 65° C. for 2 minutes to perform surface treatment.

[0101] Then, as shown in FIG. 1 in process (b), the substrate wasimmersed into an electroless copper plating solution 5 to be describedbelow without water washing. At that time, the titanium nitride layer 4on the silicon substrate surface was connected with a copper plate 7 bya conductive wire 8. The plating metal was formed on the surface of thecopper plate 7 by electroless plating. Therein, the surface area of thetitanium nitride layer 4 on the silicon substrate surface wasapproximately 30 cm² and the surface area of the copper plate 7 on boththe obverse and the reverse sides was approximately 50 cm². Byperforming the electroless copper plating for approximately 2 minutes, acopper thin film 9 was uniformly formed as a seed layer on the surfaceof the titanium nitride layer 4, and the thickness of the copper thinfilm 9 was approximately 70 nm both inside of the via-hole 3 and on thesurface, as shown in FIG. 1 in process (c).

[0102] [Electroless copper plating solution]

[0103] Copper sulfide . . . 0.04 mol/l

[0104] Ethylene-diamin-4-acetate-2-sodium . . . 0.03 mol/l

[0105] Formaldehyde . . . 0.1 mol/l

[0106] 2,2′-bipyridyl . . . 0.0002 mol/l

[0107] Polyethylene glycol (average molecular weight 600) . . . 0.03mol/l

[0108] pH=12.8

[0109] Solution temperature 70° C.

[0110] Next, the substrate having the formed copper thin film 9 wasextracted out of the electroless copper plating solution 5 and washedwith water. Then, the substrate was treated with an aqueous solution of10% dilute sulfuric acid for 2 minutes, and immersed into anelectroplating solution to perform plating. FIG. 1 in process (d) is across-sectional view showing the substrate in which the via-hole 3 isfilled with a copper conductor 10 and a copper thin film is formed abovethe insulator film 2 by electro-plating using a solution describedbelow. [Copper electroplating solution]

[0111] Copper sulfate . . . 0.3 mol/l

[0112] Sulfuric acid . . . 1.9 mol/l

[0113] Solution temperature . . . 25° C.

[0114] Successively, chemical-mechanical (CMP) polishing was performedto separate the conductor 10. FIG. 1 in process (e) is a cross-sectionalview showing the substrate after forming via-studs 12 by CMP polishing.

[0115] As described above, the, effect of the present invention can beconfirmed by the fact that the seed layer can be formed by using theplating method in accordance with the present invention without using adry method, such as the sputtering method, and a small hole can beeasily filled with copper by electroplating.

[0116] [Embodiment 2]

[0117]FIG. 2 is a process flow diagram showing an example in which thepresent invention is applied to plating for filling a hole forconnecting between layers and a trench for forming wiring.

[0118] Initially, as shown in FIG. 2 in process (a), an insulator film 2of SiO₂ was deposited on an LSI silicon substrate 1, and a via-hole 3reaching down to the LSI silicon substrate 1 and a trench 11 for formingwiring were formed in the insulator film 2.

[0119] After that, titanium nitride 4 was deposited to form a barrierlayer which covered the whole surface from the via-hole 3 to the wiringforming trench 11 and the surface of the insulator film.

[0120] Next, the substrate was immersed into an aqueous solutioncontaining EDTA of 0.1 mol/l and hydrogen peroxide of 0.08 mol/l at atemperature of 65° C. for 2 minutes to perform surface treatment.

[0121] Then, as shown in FIG. 2 in process (b), the substrate wasimmersed into an electroless copper plating solution 5 to be describedbelow without water. washing, similar to Embodiment 1. At that time, thetitanium nitride layer 4 on the silicon substrate surface was connectedwith a copper plate 7 by a conductive wire 8. Therein, the surface areaof the titanium nitride layer 4 on the silicon substrate surface wasapproximately 30 cm² and the surface area of the copper plate 7 on boththe obverse and the reverse sides was approximately 50 cm².

[0122] By performing electroless copper plating for approximately 2minutes, a copper thin film 9 was uniformly formed as a seed, layer onthe surface of the titanium nitride layer 4, and the thickness of thecopper thin film 9 was approximately 70 nm both inside of the via-hole 3and on the surface of the wiring forming trench 11, as shown in FIG. 2in process (c).

[0123] Next, the substrate having the formed copper thin film 9 wasextracted out of the electroless copper plating solution 5 and washedwith water. Then, the substrate was treated with an aqueous solution of10% dilute sulfuric acid for 2 minutes, and immersed into anelectroplating solution to perform plating. FIG. 2 in process (d)provides a cross-sectional view showing the substrate in which thevia-hole 3 is filled with a conductor 10 by electroplating using thesame solution as in Embodiment 1.

[0124]FIG. 2 in process (e) provides a cross-sectional view showing thesubstrate after forming the wiring and via-studs 12 by CMP polishing.

[0125] As described above, the effect of the present invention can beconfirmed by the fact that the seed layer can be formed by using theplating method in accordance with the present invention without using adry method, such as the sputtering method, and a small hole can beeasily filled with copper by electroplating.

[0126] [Embodiment 3]

[0127] The substrate was prepared through the same method as that ofEmbodiment 1 except for using any one of tantalum, tantalum nitride,tungsten and tungsten nitride instead of titanium nitride. As a result,a substrate having a cross-sectional structure similar to that ofEmbodiment 1 was obtained. Accordingly, the effect of the presentinvention can be confirmed by the fact that a seed layer can be formedby using the plating method in accordance with the present inventionwithout using a dry method, such as the sputtering method, and a smallhole can be easily filled with copper by electroplating.

[0128] [Embodiment 4]

[0129] An outline of the present embodiment is shown in FIG. 3. As shownin FIG. 3 in process (a), an insulator film 2 of SiO₂ was formed on anLSI silicon substrate 1 through the same method as in Embodiment 1, andvia-holes 3 were formed in the insulator film 2. After that, titaniumnitride 4 was deposited to form a barrier layer which covered the wholesurface from the via-hole 3 to the surface of the insulator film.

[0130] Next, the substrates were respectively immersed into an aqueoussolution containing EDTA of 0.1 mol/l and hydrogen peroxide of 0.08mol/l and into an aqueous solution containing EDTA of 0.1 mol/l withouthydrogen peroxide at a temperature of 65° C. for 2 minutes for theformer and 30 minutes for the latter to perform surface treatment.

[0131] Then, as shown in FIG. 3 in process (b), the substrate wasimmersed into an electroless copper plating solution 5 without waterwashing, similar to Embodiment 1. At that time, the titanium nitridelayer 4 on the silicon substrate surface was connected with a copperplate 7 by a conductive wire 8. Therein, the surface area of thetitanium nitride layer 4 on the silicon substrate surface wasapproximately 30 cm² and the surface area of the copper plate 7 on boththe obverse and the reverse sides was approximately 50 cm². Byperforming electroless copper plating for approximately 30 minutes, anelectroless copper plating of approximately 1 μm thickness was formed onthe surface of the titanium nitride layer 4.

[0132] As a result, the whole via-hole 3 was filled with the copperconductor 10, as shown in FIG. 3 in process (c).

[0133] Then, the substrate was subjected to CMP polishing to form thevia-studs 12, as shown in FIG. 3 in process (d).

[0134] As described above, the effect of the present invention can beconfirmed for both treatments by the fact that the seed layer can beformed by using the plating method in accordance with the presentinvention without using a dry method, such as the sputtering method, anda small hole can be easily filled with copper by electroplating.

COMPARATIVE EXAMPLE 1

[0135] For the purpose of comparison, an example to which the presentinvention is not applied will be described below.

[0136] A via-hole was formed in a substrate using a method similar toEmbodiment 1, and a barrier layer was formed on the substrate usingtitanium nitride. Then, the substrate was immersed into the electrolessplating solution. At that time, surface treatment using the EDTA grouptreating solution before plating was not performed on the substrate. Asa result, electroless plating reaction did not occur on the titaniumnitride surface, and accordingly no electroless copper plating film wasformed. Therefore, copper was hardly deposited onto the inside of thevia-hole by the electroplating with copper in the next process, and thevia-hole could not be filled with the metal.

[0137] In addition, a substrate was treated in a manner similar to thesubstrate in Embodiment 1 up to the pre-plating treatment with the EDTAgroup aqueous solution and then the substrate was immersed into theelectroless plating solution. At that time, the silicon substrate wassolely immersed into the electroless copper plating solution withoutconnecting the titanium nitride layer to a copper plate using aconductive wire. As a result, electroless plating reaction did not occuron the titanium nitride surface, and accordingly no electroless copperplating film was formed. Therefore, copper was hardly deposited onto theinside of the via-hole by the electroplating with copper in the nextprocess, and the via-hole could not be filled with the metal.

[0138] As described above, it was confirmed that in both of the cases ofnot applying the present invention, the object of the present inventioncould not be attained. From this fact, the effectiveness of the presentinvention can be verified.

[0139] [Embodiment 5]

[0140]FIG. 4 is a cross-sectional view showing a semiconductor device inwhich a multilayered wiring is formed by forming via-studs 12 ofEmbodiments 1 to 4 on an LSI silicon substrate 1 and by alternativelyforming a wiring layer 13 and an insulator layer 2 with via-studs 12. Asshown in the figure, W plugs 34 are formed in an insulator layer 2 onthe LSI silicon substrate 1 and then a wiring layer 13 and insulatorlayer 2 with via-studs 12 are formed thereon, that is, the insulatinglayers 2 with via-studs 12 and the wiring layers 13 are alternativelyformed. A titanium nitride layer 4 formed by Sputtering and an Al—Sialloy layer 36 formed thereon are formed on the wiring layer 13 formeduppermost. A protective film 37 made of polyimide resin is formed on thesurface of the uppermost SiO₂ insulator layer 2. The W plug 34 is formedthrough CVD processing. In the present embodiment, there are five wiringlayers 13.

[0141] [Embodiment 6]

[0142]FIG. 5 is a perspective view showing a semiconductor device of thesurface mounting type in which a semiconductor device 20 having amultilayer wiring formed on an LSI silicon substrate as obtained inEmbodiment 5 is resin sealed by epoxy resin. The epoxy resin 19 is aresin having a filler to be described below. The reference character 15indicates an Au wire, the reference character 16 indicates a dyebonding, the reference character 17 indicates an outer lead, and thereference character 18 indicates a support. Copper or 4-2 alloy is usedfor a lead frame.

[0143] Various kinds of fillers shown in Table 1 and the composition ofan epoxy resin were kneaded using a two-shaft roll heated at 80° C. for10 minutes. The resulting composition using a spherical filler is verylow in melt viscosity and large in fluidity compared to a compositionusing a cubic filler, though the gelling times are almost equal to eachother. Further, the melt viscosity becomes lower and the fluiditybecomes larger as the composition is mixed with a filler having asmaller value of gradient n expressed by an RRS particle size diagram.The filler having a value n below 0.6 is unfavorable because the meltviscosity (180° C.) is slightly increased. TABLE 1 N (composition:weight part) o. 1 2 3 4 5 o-cresol novolak type epoxy 90 90 90 90 90resin phenol bromide novolak type 10 10 10 10 10 epoxy resin phenolnovolak type epoxy 52 52 52 52 52 resin tri-phenyl-phosphine 1 1 1 1 1antimony tri-oxide 4 4 4 4 4 epoxy-silne 2 2 2 2 2 Hoechst wax 1 1 1 1 1carbon black 1 1 1 1 1 epoxy-denaturated-dimethyl- 10 10 10 10 10siloxane (denaturating agent) filler (sphere-1) n = 0.95 643 — — — —filler (sphere-2) n = 0.65 — 643 — — filler (sphere-3) n = 25 — — 643 —— filler (cubic-1) n = 1.5 — — — 643 — filler (cubic-2) n = 0.75 — — — —643 minimum melt viscosity 220 280 300 3310 2630 (poise) spiral flow(inch) 34 27 17 2 9

[0144] Furthermore, resin compositions were fabricated using thespherical filler (spher-1) by varying the adding amount to 70, 75, 80and 85 weight %, respectively.

[0145] These compositions were transfer-molded and hardened for 6 hoursat 180° C., and then the coefficients of linear expansion, the bendingcoefficients of elasticity and the thermal stresses at room temperaturewere measured.

[0146] Further, semiconductor elements having a zigzag wiring formed ofaluminum on the surface were sealed with a transfer press, andcooling-and heating cycle tests of 2000-cycle between −55° C. for 30minutes and +150° C. for 30 minutes were conducted using the sealedsemiconductor elements to, evaluate anti-crack resistance of the sealingresin layer, and the connection reliability of lead-to-gold wire bondingand aluminum wiring (it was judged to be defective when the resistancewas changed above 50%)

[0147] It can be understood from Table 2 that the compositionscontaining. silicone polymer and having a filler above 80 weight % havesmall coefficients of linear expansion below 1.3×10⁻⁵/° C. and smallincreases in coefficients of elasticity, and accordingly, the thermalstress caused by insertion is small.

[0148] The resin sealing type semiconductor device using the resincomposition in accordance with the present embodiment is excellent inanti-crack resistance and in connection reliability even if thermalshock, such as that of the cooling-and-heating test, is applied to thesemiconductor device.

[0149] In the present embodiment, the resin composition not containingsiloxane was added with a filler of a total 85 weight % which consistedof 95% of spherical quartz powder having a grain size smaller than 100μm and the remainder of cubic quartz powder having a grain size smallerthan 10 μm. The resin composition containing siloxane was added with thefiller of total 80.5 weight % which consisted of 70% of spherical quartzpowder having a grain size smaller than 100 μm and the remainder ofcubic quartz powder having a grain size smaller than 5 μm. All of theresin sealing type semiconductor devices had characteristics similar tothat of the embodiment described previously. TABLE 2 (composition:weight part) No. 6 7 8 9 10 o-cresol novolak type 90 90 90 90 90 epoxyresin phenol bromide novolak 10 10 10 10 10 type epoxy resinepoxy-denaturated- 10 10 10 10 0 dimethyl-siloxane (denaturating agent)adding amount of filler 80 85 70 75 80 (weight %) coefficient of linear1.3 1.1 2.0 1.8 1.3 expansion (× 10⁻⁵/° C.) coefficient of bending 20602170 1720 1790 2320 elasticity (kg/mm²) thermal stress (kg/mm²) 0.2 ≐00.8 0.6 0.4 anti-crack resistance 0/45 0/45 30/45 25/45 2/45 connectionreliability 0/150 0/150 70/150 45/150 5/150

[0150] The RRS particle size diagram is a particle size diagramexpressing particle size distribution according to the Rosin-Rammlerformula (Powder Technology Handbook, pages 51-53, distributed by JapanPowder Industrial Association).

R(Dp)=100 exp (−b·Dp ^(n)  (1)

[0151] There, R(Dp) is the cumulative weight percentage up to a particlesize Dp from the maximum particle size, Dp is a particle size, and b andn are constants.

[0152] The gradient in the RRS particle size diagram corresponds to thevalue n in the Rosin-Rammler formula which is expressed by a straightline connecting two points where the cumulative weight percentages fromthe maximum particle site of the RRS particle size diagram become 25%and 75%.

[0153] It is known that a particle size distribution of pulverized rawmaterial of the filler agrees with the Rosin-Rammler formula, andbecomes a nearly straight line in the RRS particle size diagramexpressing the particle size distribution based on the formula.

[0154] The inventors of the present invention have confirmed bymeasuring particle size distributions of various kinds of fillers thatall the particle size distributions of the fillers almost show linearityin the RRS particle size diagram above 90 weight percentage and wellagree with the above formula if the powder is not specially sieved.

[0155] The preferable melted quartz powder used in accordance with thepresent invention is composed of spherical particles which are formed bysupplying melt quartz powder pre-pulverized in a predetermined particlesize distribution by a constant amount into a high temperature flamegenerated from a melting apparatus using a flammable gas such aspropane, butane, acetylene, hydrogen or the like as the fuel to melt thepulverized powder and then cooling. Since the above-mentioned meltquartz itself is small in coefficient of linear expansion and very smallin ionic impurities, it is suitable for use as a resin compositionmaterial for sealing a semiconductor element.

[0156] It is preferable when the amount of the particles having aparticle size within a range of 0.5 to 100 μm is 90 weight % or more. Ifthe amount of particles having a particle size below 0.5 μm isincreased, the thixotropic property of the resin component becomes largeso as to increase the viscosity and reduce the fluidity. on the otherhand, if the amount of particles having a particle size exceeding 100 μmis increased, the Au wires of the semiconductor element are deformed orbroken and resin filling defect is likely caused by coarse particlesblocking the mold when the semiconductor element is sealed.

[0157] Further, it is preferable when the gradient n shown in the RRSparticle size diagram is set to 0.6 to 0.95. When the value of n islarger than 0.95, the volume of the filler is bulked up and accordinglythe viscosity of the resin composition is increased and the fluidity isdecreased. Therefore, it is preferable when the value n is as small aspossible. On the other hand, in accordance with the present invention,there is the condition that an amount of the particles having a particlesize within a range of 0.5 to 100 μm is preferably 90 weight % or more.The lower limit value n of 0.6 is the minimum value acceptable underthis condition.

[0158] The silicone polymer used in accordance with the presentinvention is poly-dimethyl-syloxane having a functional group such as anamino group, a carboxyl group, an epoxy group, hydroxyl group,pyrimidine group or the like in the end or the side.

[0159] Epoxy resin in a solid state at room temperature includes acresol novolak type epoxy resin, phenol novolak type epoxy resin,bis-phenol A type epoxy resin and so on as a semiconductor sealingmaterial; wherein, novolak resins, such as phenol novolak, cresolnovolak and so on, acid anhydrides, such as pyromellitic acid anhydride,benzophenone anhydride and so on, are used as the curing agent, andfurther, a curing accelerating agent, a flexibility-improving agent, acoupling agent, a coloring agent, an anti-flammable agent, a molddetaching agent and so on may be mixed if necessary.

[0160] The epoxy resin composition can be molded by kneading the rawmaterials using a two-shaft roll or an extrusion machine heated to 70 to100° C. , and by molding using a transfer press under conditions of amold temperature of 160 to 190° C., a molding pressure of 30 to 100kg/cm², and a curing time of 1 to 3 minutes.

[0161] By making the coefficient of linear expansion of the curedmaterial as small as 1.3×10⁻⁵/° C., as described previously, thecoefficient of elasticity can be also decreased. Therefore, the Au wiresof the semiconductor element are hardly deformed or broken when thesemiconductor element is sealed, and the thermal stress caused by thedifference in the coefficients of linear expansion is small. Therefore,the semiconductor device is excellent in temperature cycle resistance,thermal resistance and humidity resistance.

[0162] Since the quartz powder used as the filler is melted to make thepowder particles spherical, the bulk is decreased and; accordingly, thefiller can be easily filled in high density. Further, since the particleof the filler has no corner which may damage the semiconductor element,it is possible to prevent the characteristic of the semiconductorelement from being ill affected. Furthermore, the coefficient ofelasticity of the resin composition can be made small and the thermalstress caused by the difference in the coefficients of linear expansioncan be made smaller by mixing the silicone polymer.

[0163] [Embodiment 7]

[0164]FIG. 6 is a process flow diagram showing an example of amanufacturing process of a copper/polyimide thin film multilayer wiringsubstrate in accordance with the present invention.

[0165] Process (a): A conductor film to be used as a first metallicwiring layer composed of Cr/Cu/Cr films (Cr film: 500 Å thickness, Cufilm: 5 μm thickness) was formed on a glass ceramic substrate 21 having6 mm thickness through a sputtering method in an Ar atmosphere. Thereference character 25 indicates a though hole for connection.

[0166] Process (b): A resist pattern (positive resist) was formed on theabove-mentioned Cr/Cu/Cr film, and a first metallic wiring layer 29 wasformed through a wet etching method.

[0167] Process (c): A polyimide group bonding sheet having 20 μmthickness in a semi-cured state was press bonded as an insulator layer22 on the first metallic wiring layer 29, and then cured.

[0168] Process (d): Next, an Al film 32 having 2000 Å thickness wasformed as a dry etching mask through a vacuum vapor deposition method.

[0169] Process (e): A dry etching mask 28 for forming a via-hole througha photo-etching method was formed, and then a via-hole 27 was formedusing a parallel-plate type dry etching apparatus, not shown, of anoxygen gas plasma of 3 Pa gas pressure, 500 W RF output.

[0170] Process (f): A barrier layer 4 made of titanium nitride wasformed over the whole surface of the substrate. At that time, both thepolyimide surface and the inner surfaces of the via-hole were coveredwith the titanium nitride. After that, the substrate was treated in anaqueous solution containing EDTA as a pre-treatment similar to the caseof the Embodiment 1, and then the pre-treated substrate was subjected toelectroless copper plating through a similar method shown in FIG. 3 atprocess step (b). As a result, the via-hole was completely filled withcopper.

[0171] Process (g): Then, a via-stud 23 was formed by performing CMPpolishing in a manner similar to Embodiment 1.

[0172] The required time of the electroless copper plating for formingthe Cu via-stud of 30 μm diameter and 25 μm height was approximately 5hours.

[0173] Process (h): A second metallic wiring layer 30 was formed byforming a conductor film composed of Cr/Cu/Cr films (Cr film: 500 Åthickness, Cu film: 5 μm thickness) on the above-mentioned insulatorlayer 22 through the sputtering method and then etching the conductorfilm, similar to the process (a) and the process (b).

[0174] By repeating the processes described above, a thin filmmultilayer wiring substrate having three or more layers can bemanufactured.

[0175] [Embodiment 8]

[0176]FIG. 7 is a schematic cross-sectional view showing a mountingstructure in which an LSI 20, having the multilayer wiring formed inEmbodiment 5 on the surface, is mounted on a thin-film multilayer wiringsubstrate 34 obtained in the present embodiment. A thin film wiringlayer made of polyimide and copper was formed on a ceramic substrate 35,and using solder bumps 26, the LSI 20 having the multilayer wiring wasmounted on and connected to the thin-film multilayer wiring substrate 34having a via-stud 23 connection. The wiring layer 24, the via-stud 23and the insulator layer 22 were manufactured through a method similar tothat in Embodiment 7.

[0177] [Embodiment 9]

[0178]FIG. 8 is a schematic cross-sectional view showing an example of amounting in which the thin film multilayer wiring substrate mounting theLSI described above is applied to a large-scaled computer board. In theexample, a module substrate 42 of the pin-inserting type is mounted on alarge printed wiring board 41.

[0179] The module substrate 42 is made of a multilayer sintered bodycomposed of glass ceramic and copper layers, and has connecting pins 43on the bottom surface. The thin film multilayer substrate 44 inaccordance with the present invention is formed on the module substrate42, and the LSI 20 is connected to and mounted on the thin filmmultilayer substrate 44 via the solder bumps 26.

[0180] According to the mounting substrate of the present embodiment,the number of wires can be reduced to approximately ¼ compared to thatin a conventional one, and the wiring density can be increased. Further,the signal transmission speed can be increased to approximately 1.5times as fast as that in the conventional one.

[0181] The thin film multilayer wiring substrate of the presentembodiment can attain speed-up of signal transmission by high densitymounting and short wiring. Further, by employing the sheet-shapedinsulator layer (for example, the polyimide group complex sheetdescribed above), the manufacturing process can be substantiallyshortened.

[0182] [Embodiment 10]

[0183]FIG. 9 is a cross-sectional view showing a semiconductor device inwhich solder balls 38 are formed on a multilayered wiring layer of thesemiconductor device having the multilayered wiring layer formed in FIG.4. The solder ball 38 is made of Au.

[0184]FIG. 10 is a cross-sectional view showing the structure of a flipchip mounting in which the semiconductor device of FIG. 9 is bonded to alarge-scaled printed wiring board 41 by the above-mentioned solder balls38. The gap between the large-scaled printed wiring board 41 and thesemiconductor device is filled with an under filler made of epoxy resinafter bonding them with the solder balls 38, as shown in the figure. Inthe present embodiment, the via-stud 12 having a diameter of 0.3 μmdescribed Embodiments 1 to 4 and the wiring layer 13 are alsoalternatively formed, as shown in FIG. 9.

[0185] [Embodiment 11]

[0186]FIG. 11 is a cross-sectional view showing a ball grid array typesemiconductor device. The present embodiment also employs thesemiconductor device 1 having the multilayered wiring layer obtained inEmbodiment 5. The above-mentioned semiconductor device 1 is bonded to abase body 47 made of a ceramic or the like with an adhesive 45 made of aresin or the like and is bonded by an Au wire 15 to an inner lead 46. Anelectrode 48 is formed by successively forming a titanium nitride layerand an Al—Si alloy layer on a Cu wire, and is pole-bonded on thesemiconductor element and wedge-bonded to the inner lead 46. Anelectrode 40 is formed by plating Sn on the Cu wire.

[0187] According to the present invention, since very small depressedportions on a substrate can be directly filled through electrolessplating without forming a seed layer through a dry metallizing methodsuch as a conventional sputtering method, high density wiring can berealized.

[0188] In addition, a seed layer having a excellent depositionuniformity with regard to the very small depressed portions on thesubstrate and without elution of the barrier layer accompanied byprogress of plating reaction is formed through electroless plating, andthen the very small depressed portions on the substrate having the seedlayer formed thereon are filled by electroplating. Therefore, it ispossible to form a fine wiring which is stable in quality.

[0189] Thereby, it is possible to form high density wiring of stablequality on a substrate, and accordingly to obtain a semiconductordevice, a module and a large-scaled computer having high reliability.

[0190] The thin film multilayer wiring substrate of the presentembodiment is advantageous for use as a substrate for a large-scaledcomputer, a substrate for a workstation and a substrate for asmall-scaled electronic apparatus, such as a video-camera and so on.

What is claimed is:
 1. A semiconductor device comprising an insulatorlayer having at least one of a via-hole for forming a via-stud and atrench for forming a wire on a semiconductor substrate, wherein said oneof the via-stud and the wire is formed in said one of the via-hole andthe trench through a barrier layer made of any one of an inorganiccompound and a high melting point metal formed on inner surfaces of saidone of the via-hole and the trench, said one of the via-stud and thewire being formed of the same metal as a metal composing the barrierlayer.
 2. A semiconductor device comprising insulator layers having avia-stud and insulator layers having a wire on a semiconductorsubstrate, said insulator layers having said via-stud and said insulatorlayers having said wire being alternately formed, wherein said via-studand said wire are respectively formed in a via-hole and a trench throughbarrier layers made of any one of an inorganic compound and a highmelting point metal formed on inner surfaces of the via-hole and thetrench, respectively, said via-stud and said wire being formed of thesame metal as a metal composing the barrier layer.
 3. A semiconductordevice comprising an insulator layer having at least one of a via-holefor forming a via-stud and a trench for forming a wire on asemiconductor substrate, wherein said one of the via-stud and the wireis formed in at least said one of the via-hole and the trench throughbarrier layers made of any one of an inorganic compound and a highmelting point metal formed on inner surfaces of said one of the via-holeand the trench, said one of the via-stud and the wire being formed ofthe same metal as a metal composing the barrier layer throughelectroplating after electroless plating of the same metal.
 4. Asemiconductor device comprising an insulator layer having at least oneof a via-hole for forming a via-stud and a trench for forming a wire ona semiconductor substrate, wherein said one of the via-stud and the wireis formed in said one of the via-hole and the trench through barrierlayers made of any one of an inorganic compound and a high melting pointmetal formed on inner surfaces of said one of the via-hole and thetrench, the whole of said one of the via-stud and the wire being formedthrough electroless plating.
 5. A semiconductor device comprisinginsulator layers having a via-stud and insulator layers having a wire ona semiconductor substrate, said insulator layers having the via-stud andsaid insulator layers having the wire being alternately formed, whereinsaid via-stud and said wire are respectively formed in a via-hole and atrench through barrier layers made of any one of an inorganic compoundand a high melting point metal formed on inner surfaces of the via-holeand the trench, respectively, said via-stud and said wire being formedof the same metal as a metal composing the barrier layer throughelectroplating after electroless plating of the same metal.
 6. Asemiconductor device comprising insulator layers having a via-stud andinsulator layers having a wire on a semiconductor substrate, saidinsulator layers having said via-stud and said insulator layers havingsaid wire being alternately formed, wherein said via-stud and said wireare respectively formed in a via-hole and a trench through barrierlayers made of any one of an inorganic compound and a high melting pointmetal formed on inner surfaces of the via-hole and the trench,respectively, an entirety of said via-stud and an entirety said wirebeing formed through electroless plating.
 7. A semiconductor devicecomprising an insulator layer having a via-stud on a semiconductorsubstrate, wherein said via-stud is formed in a via-hole through abarrier layer made of any one of an inorganic compound and a highmelting point metal formed on an inner surface of the via-hole, adiameter of said via-stud being smaller than 0.3 μm.
 8. A resin sealedsemiconductor device comprising a semiconductor device according toclaim 7 which is sealed by a composition containing epoxy resin,spherical quartz particles and silicone polymer.
 9. A resin sealedsemiconductor device according to claim 8, wherein said spherical quartzparticles are contained in the composition in an amount of more than 80weight % of the total weight of said composition.
 10. A modulecomprising a multilayer thin film wiring substrate composed of aplurality of laminated insulator layers, each of said insulator layershaving a wiring layer on a surface; and a semiconductor device mountedon said wiring substrate, wherein said semiconductor device is thesemiconductor device according to claim
 9. 11. A large-scaled computercomprising a module substrate mounted on a printed wiring board, saidmodule substrate being connected to said printed wiring board throughconnecting pins; a multilayer thin film wiring substrate mounted on saidmodule substrate, said multilayer thin film wiring substrate having aplurality of laminated insulator layers, each of the insulator layershaving a wiring layer; and the semiconductor device according to claim 9mounted on said wiring substrate.
 12. A resin sealed semiconductordevice comprising a semiconductor device according to claim 1 which issealed by a composition containing epoxy resin, spherical quartzparticles and silicone polymer.
 13. A resin sealed semiconductor deviceaccording to claim 12, wherein said spherical quartz particles arecontained in the composition in an amount of more than 80 weight % ofthe total weight of said composition.
 14. A module comprising amultilayer thin film wiring substrate composed of a plurality oflaminated insulator layers, each of said insulator layers having awiring layer on a surface; and a semiconductor device mounted on saidwiring substrate, wherein said semiconductor device is the semiconductordevice according to claim
 13. 15. A large-scaled computer comprising amodule substrate mounted on a printed wiring board, said modulesubstrate being connected to said printed wiring board throughconnecting pins; a multilayer thin film wiring substrate mounted on saidmodule substrate, said multilayer thin film wiring substrate having aplurality of laminated insulator layers, each of the insulator layershaving a wiring layer; and the semiconductor device according to claim13 mounted on said wiring substrate.
 16. A resin sealed semiconductordevice comprising a semiconductor device according to claim 2 which issealed by a composition containing epoxy resin, spherical quartzparticles and silicone polymer.
 17. A resin sealed semiconductor devicecomprising a semiconductor device according to claim 3 which is sealedby a composition containing epoxy resin, spherical quartz particles andsilicone polymer.
 18. A resin sealed semiconductor device comprising asemiconductor device according to claim 4 which is sealed by acomposition containing epoxy resin, spherical quartz particles andsilicone polymer.
 19. A resin sealed semiconductor device comprising asemiconductor device according to claim 5 which is sealed by acomposition containing epoxy resin, spherical quartz particles andsilicone polymer.
 20. A resin sealed semiconductor device comprising asemiconductor device according to claim 6 which is sealed by acomposition containing epoxy resin, spherical quartz particles andsilicone polymer.